HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 299

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

10.2.5
SCI1 can generate an interrupt at the end of a data transfer.
When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 2 (IRR2) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 2
(IENR2).
For further details, see 3.3, Interrupts.
10.3
10.3.1
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 12 data transfer formats.
Data length
Stop bit length
Parity
Multiprocessor bit
Receive error detection
Break detection
Interrupts
SCI3
Overview
7 or 8 bits
1 or 2 bits
Even, odd, or none
“1” or “0”
Parity, overrun, and framing errors
Break detected by reading the RXD pin level directly when
a framing error occurs
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