HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 70

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
Reset by Watchdog Timer: The watchdog timer counter (TCW) starts counting up when the
WDON bit is set to 1 in the watchdog timer control/status register (TCSRW). If TCW overflows,
the WRST bit is set to 1 in TCSRW and the chip enters the reset state. While the WRST bit is set
to 1 in TCSRW, when TCW overflows the reset state is cleared and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see 9.1.1, Watchdog Timer.
60
RES
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
Vector fetch
Reset cleared
(2)
(1)
Internal
processing
Program initial
instruction prefetch
(2)
(3)