HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 69

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

3.1
Exception handling is performed in the H8/3644 Series when a reset or interrupt occurs. Table 3.1
shows the priorities of these two types of exception handling.
Table 3.1
Priority
High
Low
3.2
3.2.1
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2
Reset by RES Pin: As soon as the RES pin goes low, all processing is stopped and the chip enters
the reset state.
To make sure the chip is reset properly, observe the following precautions.
Reset exception handling begins when the RES pin is held low for a given period, then returned to
the high level.
Reset exception handling takes place as follows.
At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
Overview
Reset
Overview
Reset Sequence
Exception Source
Reset
Interrupt
Exception Handling Types and Priorities
Section 3 Exception Handling
Time of Start of Exception Handling
Exception handling starts as soon as the reset state is cleared
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling
in progress is completed
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