HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 110

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.6
5.6.1
Subactive mode is entered from watch mode if a timer A or IRQ
LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A,
IRQ
place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable
register.
5.6.2
Subactive mode is cleared by a SLEEP instruction or by input at the RES pin.
5.6.3
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are ø
Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer,
below.
Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
3
W
to IRQ
/2, ø
Subactive Mode
Transition to Subactive Mode
Clearing Subactive Mode
Operating Frequency in Subactive Mode
W
0
/4, and ø
, or INT
W
7
to INT
/8.
0
interrupt is requested. A transition to subactive mode does not take
0
interrupt is requested while the
101