HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 256

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Table 9.16 Input Edge Selection during Buffer Operation
IEDGA
0
1
ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is
transferred from them to the CPU via a temporary register (TEMP). For details see 9.5.3, CPU
Interface.
To assure input capture, the pulse width of the input capture input signal must be at least 1.5
system clocks (ø) when a single edge is selected, or at least 2.5 system clocks (ø) when both edges
are selected.
ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep
mode, and subactive mode.
248
FTIA
IEOGA BUFEA IEDGC
IEDGC
0
1
0
1
Edge detector
capture signal
and internal
generator
ICRC
Input Edge Selection
Falling edge of input capture A input signal is captured
Rising and falling edge of input capture A input signal are both captured
Rising edge of input capture A input signal is captured
Figure 9.17 Buffer Operation (Example)
ICRA
FRC
(initial value)