HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 175

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HD6433640

Manufacturer Part Number
HD6433640
Description
H8/3644 Series Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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7. Design a current margin into the programming voltage (V
8. Insure that peak overshoot at the FV
9. Use the recommended algorithms when programming and erasing flash memory.
10. For comments on interrupt handling while flash memory is being programmed or erased, see
11. Notes on accessing flash memory control registers
166
12 V
Insure that V
programming and erasing. Programming and erasing may become impossible outside this
range.
Connect bypass capacitors as close as possible to the FV
In boot mode start-up, also, bypass capacitors should be connected to the TEST pin in the same
way.
The recommended algorithms enable programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
program (P) or erase (E) bit in the flash memory control register (FLMCR), the watchdog
timer should be set beforehand to prevent the specified time from being exceeded.
section 6.7.9, Interrupt Handling during Flash Memory Programming/Erasing.
a. Flash memory control register access state in each operating mode
The H8/3644F, H8/3643F, and H8/3642AF have flash memory control registers located at
addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can
only be accessed when 12 V is applied to the flash memory programming power supply
pin, FV
1.0 F
PP
PP
.
Figure 6.26 Example of V
remains within the range 12.0 V 0.6 V (11.4 V to 12.6 V) during
PP
0.01 F
and TEST pins does not exceed the maximum rating.
PP
Power Supply Circuit Design
PP
PP
and TEST pins.
) power supply.
FV
PP
H8/3644F

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