HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 293

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bits 4 to 2—Reserved Bits: Bits 4 to 2 are reserved. They are always read as 0, and cannot be
modified.
Bit 1—TAIL MARK Transmit Flag (MTRF): When bit MRKON is set to 1, bit 1 indicates that
TAIL MARK is being sent. Bit 1 is a read-only bit and cannot be modified.
Bit 1: MTRF
0
1
Bit 0—Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to
start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0: STF
0
1
Serial Data Register U (SDRU)
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this register
is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is not fixed.
Bit
Initial value
Read/Write
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
SDRU7
Description
Idle state, or 8- or 16-bit data is being transferred
TAIL MARK is being sent
Description
Read: Indicates that transfer is stopped
Write: Invalid
Read: Indicates transfer in progress
Write: Starts a transfer operation
R/W
7
SDRU6
R/W
6
SDRU5
R/W
5
SDRU4
R/W
4
SDRU3
R/W
3
SDRU2
R/W
2
SDRU1
R/W
1
(initial value)
(initial value)
SDRU0
R/W
0
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