HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 77

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Interrupt Enable Register 2 (IENR2)
IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR2
is initialized to H'00.
Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT
0
1
Bit 6—A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter
interrupt requests.
Bit 6: IENAD
0
1
Bit 5—Reserved Bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4—SCI1 Interrupt Enable (IENS1): Bit 4 enables or disables SCI1 transfer complete
interrupt requests.
Bit 4: IENS1
0
1
Bits 3 to 0—Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
Bit
Initial value
Read/Write
IENDT
R/W
Description
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
Description
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
Description
Disables SCI1 interrupt requests
Enables SCI1 interrupt requests
7
0
IENAD
R/W
6
0
—
—
5
0
IENS1
R/W
4
0
—
—
3
0
—
—
2
0
—
—
1
0
(initial value)
(initial value)
(initial value)
—
—
0
0
67