HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 307

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Serial Control Register 3 (SCR3)
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode.
Bit 7—Transmit interrupt Enable (TIE): Bit 7 selects enabling or disabling of the transmit data
empty interrupt request (TXI) when transmit data is transferred from the transmit data register
(TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to
1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7: TIE
0
1
Bit 6—Receive Interrupt Enable (RIE): Bit 6 selects enabling or disabling of the receive data
full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is
transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF
in the serial status register (SSR) is set to 1. There are three kinds of receive error: overrun,
framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6: RIE
0
1
Bit
Initial value
Read/Write
R/W
Description
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
Description
Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt request
(ERI) enabled
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(initial value)
(initial value)
CKE0
R/W
0
0
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