HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 109

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

5.5
5.5.1
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A is
halted. As long as a minimum required voltage is applied, the contents of CPU registers, the on-
chip RAM and some registers of the on-chip peripheral modules are retained. I/O ports keep the
same states as before the transition.
5.5.2
Subsleep mode is cleared by an interrupt (timer A, IRQ
RES pin.
100
Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
Subsleep Mode
Transition to Subsleep Mode
Clearing Subsleep Mode
3
to IRQ
0
, INT
7
to INT
0
) or by input at the