HD6433640 HITACHI [Hitachi Semiconductor], HD6433640 Datasheet - Page 80

• Manufacturer Part Number: HD6433640
• Description: H8/3644 Series Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Interrupt Request Register 2 (IRR2)
Note: * Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, or SCI1 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR2 is
initialized to H'00.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT
0
1
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6: IRRAD
0
1
Bit 5—Reserved bit: Bit 5 is reserved: it is always read as 0 and cannot be modified.
Bit 4—SCI1 Interrupt Request Flag (IRRS1)
Bit 4: IRRS1
0
1
Bits 3 to 0—Reserved Bits: Bits 3 to 0 are reserved: they are always read as 0 and cannot be
modified.
70
Bit
Initial value
Read/Write
IRRDT
R/W*
Description
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2
Description
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Description
Clearing conditions:
When IRRS1 = 1, it is cleared by writing 0
Setting conditions:
When an SCI1 transfer is completed
7
0
IRRAD
R/W*
6
0
—
—
5
0
IRRS1
R/W*
4
0
—
—
3
0
—
—
2
0
—
—
1
0
(initial value)
(initial value)
(initial value)
—
—
0
0