s5u1c33000c Epson Electronics America, Inc., s5u1c33000c Datasheet - Page 446

• Manufacturer Part Number: s5u1c33000c
• Description: Cmos 32-bit Single Chip Microcomputer S5u1c33000c Manual
• Manufacturer: Epson Electronics America, Inc.

CHAPTER 16: DEBUGGER
430
The following lists the contents of trace information displayed in ICE mode:
Cycle:
Address:
Code:
Unassemble: Disassembled content of the fetched instruction.
Address:
Data:
Clk:
Type:
TRC:
T:
File:
Line:
SourceCode: Source code (displayed only when source display is selected by the tm command).
Trace cycle (decimal). The last information taken into the trace memory becomes 00000.
CPU-instruction-fetch address (hexadecimal).
"--------" is displayed for a non instruction-fetch access.
Instruction code fetched by the CPU (hexadecimal).
"----" is displayed for a non instruction-fetch access.
"--------" is displayed for a non instruction-fetch access.
Address accessed by the CPU (hexadecimal).
"--------" is displayed for an instruction-fetch access.
Read/write data (hexadecimal).
"----" is displayed for an instruction-fetch access.
Number of clocks used in the bus operation (1 to 7).
"V" is displayed when 8 or more clocks are used.
Bus operation type:
Access size:
Memory type:
Input to TRCIN pin (denoted by L when low-level signal is input).
Trace trigger point (placed at the beginning of the line).
Displayed only for the bus cycle that meets trace trigger conditions.
Source file name (displayed only when source display is selected by the tm command).
Source line number (displayed only when source display is selected by the tm command).
Inst: Instruction fetch, VecR: Vector read, DatR: Data read, DatW: Data write
StkR: Stack read, StkW: Stack write, DmaR: DMA read, DmaW: DMA write
B: Byte access, H: Half word access, W: Word access
SRAM, DRAM, BROM (burst ROM), IRAM (internal RAM), I/O (internal I/O)
DBUG (for ICE development), ERR (others)
EPSON
(C COMPILER PACKAGE FOR S1C33 FAMILY) (Ver. 4)
S5U1C33000C MANUAL