s5u1c33000c Epson Electronics America, Inc., s5u1c33000c Datasheet - Page 331

• Manufacturer Part Number: s5u1c33000c
• Description: Cmos 32-bit Single Chip Microcomputer S5u1c33000c Manual
• Manufacturer: Epson Electronics America, Inc.

Notes: • In the S5U1C33104H, a bus access to the internal RAM area does not generate a map break
CE break and Map break on ICD+MEM mode
The following two break functions are set by memory map information in the parameter file.
(1) CE break
(2) Map break
Notes: • If the bus’s operating frequency exceeds 30 MHz, the "no CE" break tends to occur
S5U1C33000C MANUAL
(C COMPILER PACKAGE FOR S1C33 FAMILY) (Ver. 4)
(4) Execution of an illegal instruction (only in the simulator mode)
A break occurs when an illegal instruction (code not generated by the Assembler as33 in which case the
instruction is marked by "*" in disassemble display) is executed in simulator mode.
When this break occurs, the db33 displays the following message in the [Command] window and stands by
waiting for command input.
S5U1C33001M1 contains the CE break function.
Each of the CE is assigned an attribute (R/W, Read Only, or Cannot be accessed) and a break occurs if the
access is illegal. When this break occurs, the db33 displays the following message in the [Command]
window and stands by waiting for command input.
S5U1C33001M1 contains the map break function.
It changes the attributes to enable/disable access to each 32KB area. Break occurs when there is an illegal
access. When this break occurs, the db33 displays the following message in the [Command] window and
stands by waiting for command input.
• For microcomputers that do not have address pins or the CE pin, CE break and map break
• For both CE and map breaks, as with bus and area breaks, a break does not actually occur
• The area into which the S5U1C33001M1’s break function is mapped (by default, the CE9 area)
• If the CPU is cold-reset while it is executing the program in ICE, ICD or debug monitor mode,
inadvertently. A "no CE" break occurs when RD or WR access is attempted while CE is not
selected. In such a case, write ;!MEM33_NOCE_DISABLE in the parameter file (or generate it
by selecting wb33’s parameter file generator option) to disable the "no CE" break.
cannot be used. Write ;!MEM33_MAP_DISABLE and ;!MEM33_CE_DISABLE in the
parameter file to disable these breaks. Note that area break also cannot be used. Bus break
can be used providing the address bits that do not have the corresponding pins are masked.
until the bus is accessed two to three times after the access occurred that met the break
conditions. This is because the S5U1C33001M1’s break function is pipelined based on bus
access.
is used exclusively for the break registers, so that no other devices can be mapped into this
area. Breaks cannot be set in this area.
or sequential break, since it cannot be detected from outside the chip. However, a no-map
area break can occur when instructions are executed in the internal RAM.
the on-chip-supported hardware PC break point (including temporary break used in the go
command or internal next operation) and the data break condition are cleared. When the
program execution breaks by another break factor, the break conditions are set again. Be
aware that no hardware PC or data breaks will occur until the conditions are reset.
EPSON
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