s5u1c33000c Epson Electronics America, Inc., s5u1c33000c Datasheet - Page 332

• Manufacturer Part Number: s5u1c33000c
• Description: Cmos 32-bit Single Chip Microcomputer S5u1c33000c Manual
• Manufacturer: Epson Electronics America, Inc.

CHAPTER 16: DEBUGGER
16.9.7 Trace Functions
The db33 has a function to trace program execution.
Note that the method of operation and functionality differ depending on the debugger mode.
Trace function in ICE mode
316
(1) Trace memory and trace information
The S5U1C33104H contains trace memory. When the program executes instructions in the trace range
according to the trace mode, the trace information on each bus cycle is taken into this memory. The trace
memory has the capacity to store information for 32768 cycles. When the trace information exceeds this
capacity, the data is overwritten, the oldest data first, unless operating in single-delay trigger mode.
Consequently, the trace information stored in the trace memory is always within 32768 cycles. The trace
memory is cleared when a program is executed, starting to trace the new execution data.
The following lists the trace information that is taken into the trace memory in every bus cycle. This list is
corresponded to display in the [Trace] window.
Cycle:
Address:
Code:
Unassemble: Disassembled content of the fetched instruction
Address:
Data:
Clk:
Type:
TRC:
T:
File:
Line:
SourceCode: Source code (displayed only when source display is selected by the tm command)
Trace cycle (decimal) The last information taken into the trace memory becomes 00000.
CPU-instruction-fetch address (hexadecimal)
"--------" is displayed for a non instruction-fetch access.
Instruction code fetched by the CPU (hexadecimal)
"----" is displayed for a non instruction-fetch access.
"--------" is displayed for a non instruction-fetch access.
Address accessed by the CPU (hexadecimal)
"--------" is displayed for an instruction-fetch access.
Read/write data (hexadecimal)
"----" is displayed for an instruction-fetch access.
Number of clocks used in the bus operation (1 to 7)
"V" is displayed when 8 or more clocks are used.
Bus operation type:
Access size:
Memory type:
Input to TRCIN pin (denoted by L when low-level signal is input)
Trace trigger point (placed at the beginning of the line)
Displayed only for the bus cycle that meets trace trigger conditions.
Source file name (displayed only when source display is selected by the tm command)
Source line number (displayed only when source display is selected by the tm command)
Inst: Instruction fetch, VecR: Vector read, DatR: Data read, DatW: Data write
StkR: Stack read, StkW: Stack write, DmaR: DMA read, DmaW: DMA write
B: Byte access, H: Half word access, W: Word access
SRAM, DRAM, BROM (burst ROM), IRAM (internal RAM), I/O (internal I/O)
DBUG (for ICE development), ERR (others)
EPSON
(C COMPILER PACKAGE FOR S1C33 FAMILY) (Ver. 4)
S5U1C33000C MANUAL