peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 97

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Functional Description
The S
-bit error indication counter CRC2 (16 bits) counts either the received bit
a
sequence 0010
and 0011
or two user programmable values defined in register VCRC
B
B
in every submultiframe on a selectable S
-bit. In the primary rate access digital section
a
CRC errors detected at T-reference points are reported via S
. Incrementing is only
a6
possible in the multiframe synchronous state.
4.7.2.5
E-Bit Access
Due to signalling procedures, the E-bits of frame 13 and frame 15 of the CRC-4
multiframe can be used to indicate received errored submultiframes:
no CRC error : E = ’1’
CRC error
: E = ’0’
Standard Procedure
E-bits of the service word are replaced by values of bit XSP.XS13 and XSP.XS15.
Automatic Procedure
Values programmed in register Status information of received submultiframes is
automatically inserted in E-bit position of the outgoing CRC-4 Multiframe without any
further interventions of the microprocessor.
In the double- and multiframe asynchronous state the E-bits are set to zero. In the
multiframe synchronous state the E-bits are processed according to ITU-T G.704.
Submultiframe Error Indication Counter
The Error Bit Counter counts zeros in E-bit position of frame 13 and 15 of every received
CRC-4 multiframe. This counter option gives information about the outgoing transmit line
if the E-bits are used by the remote end for submultiframe error indication. Incrementing
is only possible in the multiframe synchronous state.
Data Sheet
97
05.2001