peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 302

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

D2RSTAT
DS2 Receive Status Register
Access
Address
Reset Value
Each bit in the DS2 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0
1
The change of status bit can also be used to generate a DS2 interrupt vector. See also
register D2RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS2 framer interrupts on page
on Page
AISS
REDS
Data Sheet
15
0
0
137.
0
: read
: 230
: 0001
: 0011
: Depends on time register will be read after reset.
: Status register will change after some clock cycles becaues REDS
: (loss of frame alignment) will be set, because no signal is available.
The named status is not or no longer existing.
The named status is currently effective.
DS2 AIS Alarm State (unframed all ‘1’s pattern)
AIS is considered valid in a multiframe when fewer than 5 zeros are
detected. At 10
signal without any bit errors has at least 5 zeros.
The AIS flag nominally changes when the AIS condition is persistent as
per alarm timing parameters defined in register D2RAP. The exact time
necessary to change the flag could be greater in extremely high error
rates. The AIS state is integrated by incrementing or decrementing a
counter at the end of each multiframe depending on the AIS condition
being valid or invalid respectively.
DS2 Red Alarm State (loss of frame alignment).
0
H
H
H
(PCI), 98
(Immediately after reset)
(After some clock cycles)
0
0
-3
H
error rates, 1 zero per multiframe is typical. A valid DS2
(Local bus)
0
0
302
0
0
AISS REDS RES RAS COFA FAS
5
4
“Layer One Interrupts”
Register Description
3
2
PEB 3456 E
1
05.2001
0