peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 148

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Interface Description
transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY
is asserted can FRAME be deasserted, which occurs on clock 8.
•
1
2
3
4
5
6
7
8
CLK
FRAME
AD
Address
Data 1
Data 2
Data 3
C/BE
Command
BE's
IRDY
TRDY
DEVSEL
Address
Data
Data
Data
phase
phase
phase
phase
Bus transaction
Figure 5-1
PCI Read Transaction
5.1.2
PCI Write Transaction
The transaction starts when FRAME is activated (clock 1 in Figure 5-2). A write
transaction is similar to a read transaction except no turnaround cycle is required
following the address phase. In the example, the first and second data phases complete
with zero wait cycles. The third data phase has three wait cycles inserted by the target.
Both initiator and target insert a wait cycle on clock 5. In the case where the initiator
inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are
withdrawn. The last data phase is characterized by IRDY being asserted while the
FRAME signal is deasserted. This data phase is completed when TRDY goes active
(clock 8).
Data Sheet
148
05.2001