peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 284

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

D3RSTAT
DS3 Receive Status Register
Access
Address
Reset Value
Each bit in the DS3 framer receive status register declares a specific condition
dependent on the selected modes. The following convention applies to the individual
bits:
0
1
Except for COFA every bit can be used to generate a DS3 interrupt vector. See also
register D3RIMSK which describes how to enable/disable interrupt vector generation
and refer to the description of DS3 framer interrupts on page
on Page
LRXC
LTXC
RSDL
TSDL
Data Sheet
15
0
LRXC LTXC RSDL TSDL LPCD SEC
14
137.
13
: read
: 1D4
: 0841
: 084D
: Depends on time register will be read after reset.
: Status register will change after some clock cycles becaues LOSS
: (loss of signal) and REDS (loss of frame alignment) will be set
: because no signal is available.
The named status is not or no longer existing.
The named status is currently effective.
Loss of Receive DS3 Clock
This bit indicates loss of DS3 receive clock.
Loss of Transmit DS3 Clock
This bit indicates loss of DS3 transmit clock.
Receive Spare Data Link Buffer Full
This bit indicates that the spare data link receive buffer (register
D3RSDL) is full.
Transmit Spare Data Link Buffer Empty
12
H
H
H
(PCI), 6A
(Immediately after reset)
(After some clock cycles)
11
10
H
(Local bus)
9
AICC
N
8
r
284
AIC
7
XBIT IDLES AISS REDS LOSS COFA FAS
6
5
4
“Layer One Interrupts”
Register Description
3
2
PEB 3456 E
1
05.2001
0