peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 288

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

D3RSDL
DS3 Receive Spare Data Link Register
Access
Address
Reset Value
DL(S)(B)
Data Sheet
15
0
0
0
: read
: 1DC
: 01FF
Overhead Bit for Block B of Subframe S
These bits buffer the spare DL bits received in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every multiframe to synchronize reading of this register. The register
must be read within 106 sec to avoid an overrun.
0
H
H
(PCI), 6E
0
0
H
(Local bus)
0
DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
8
288
7
6
5
4
Register Description
3
2
PEB 3456 E
1
05.2001
0