peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 363

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

RCR2
Receive Channel Configuration Register 2
Access
Address
Reset Value
PAS
SAUM
SAUP
Data Sheet
PAS SAUM SAUP
15
14
13
: read/write
: 01
: 0000
Pattern Select for SSM and CRC Count Function
This bit selects the default pattern for synchronization status messages
and bit error indication.
0
1
S
This bit selects the update mode for the S
RSAW1..RSAW3.
E1: Doubleframe
0
1
E1: CRC-4 Multiframe
0
1
S
This bit enables the S
0
1
a
a
-bit Update Mode
-Bit Update
12
H
SACRC(2:0)
H
Use pattern defined in ETS 300233.
Use patterns specified in registers VSSM and VCRC.
S
S
eight frames.
S
S
a multiframe start.
Disable update of S
Enable update of S
a
a
a
a
-bits are updated after eight frames.
-bits are updated only, if S
-bits are updated after every multiframe.
-bits are updated only, if S
10
9
SASSM(2:0)
a
-bit update function.
363
a
a
-bits using RSAW1..RSAW3 registers.
-bits.
7
SA8E SA7E SA6E SA5E SA4E SMF T1E1
a
6
a
data changes. Update is done after
data changes. Update is done on
5
4
a
-bits located in register
Register Description
3
2
PEB 3456 E
1
05.2001
0