peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 88

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

4.6.4.3
The TE3-CHATT generates and detects a framed or unframed in-band loop up/actuate
(00001) and down/deactuate (001) pattern according to ANSI T1.403 even in the
presence of bit error rates as high as 1/100. Replacing the transmit data with the in-band
loop codes is done by TCMDR.XLD / XLU for actuate or deactuate loop code.
The CPU must reset this bit to 0 for normal operation (no loop-back code). The TE3-
CHATT also offers the ability to generate and detect a flexible in-band loop up/actuate
and down/deactuate pattern. The loop up and down pattern is individual programmable
in the Loop Code Register from 5 to 8 bits in length.
Status and interrupt-status bits will inform the user whether Loop Actuate- or Deactuate
code was detected, but the CPU must activate the loop-back.
4.6.4.4
The framer examines the receive data stream of each port on the pulse density
requirement defined by ANSI T1. 403. More than 15 consecutive zeros or less than N
ones in each and every time window of 8(N+1) data bits, where N=23 will be detected.
Violations of these rules are indicated by setting the status bit FRS.PDEN. Moreover the
PDEN bit in the interrupt vector will be set.
4.6.4.5
The TE3-CHATT supports the error performance monitoring by detecting following
alarms in the received data.
• Framing errors
• CRC errors
• Loss of frame alignment
• Loss of signal
• Alarm indication signal
Loss of frame alignment, Loss of signal and AIS are indicated with interrupt status bits.
With a programmable interrupt mask (register IMR) all these error events could generate
an Errored Second interrupt (ES) if enabled. Additionally a one Second interrupt could
be generated to indicate that the ES interrupt has to be read. If the ES interrupt is set the
enabled alarm status bits or the error counters have to be examined.
The following counters are implemented in the T1 framer:
• Framing Error Counter: This counter will be incremented when incorrect FT and FS
• CRC Error Counter (Only ESF mode): The counter will be incremented when a
Data Sheet
bits in SF mode or incorrect FPS bits in ESF format are received. Framing errors will
not be counted during asynchronous state.
multiframe has been received with a CRC error. CRC errors will not be counted during
asynchronous state.
In-Band Loop Generation and Detection
Pulse Density Detection
Error Performance Monitoring
88
Functional Description
PEB 3456 E
05.2001