peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 275

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

D3TSDL
DS3 Transmit Spare Data Link Register
Access
Address
Reset Value
Multiframe buffer for spare DL bits transmitted in blocks 3, 5, and 7 of subframes 2, 6,
and 7. If enabled, the M13 will generate an interrupt every multiframe to request a refresh
of this register. The software must write these registers within 106 sec to avoid an
underrun.
DL(S)(B)
Data Sheet
15
0
0
0
: read/write
: 1A4
: 01FF
Overhead bit for block B of subframe S
These bits store the DL bits to be transmitted in blocks 3, 5, and 7 of
subframes 2, 6, and 7. If enabled, the M13 will generate an interrupt
every multiframe to request a refresh of this register. The software must
write these registers within 106 sec to avoid an underrun.
0
H
H
(PCI), 52
0
0
H
(Local bus)
0
DL77 DL75 DL73 DL67 DL65 DL63 DL27 DL25 DL23
8
275
7
6
5
4
Register Description
3
2
PEB 3456 E
1
05.2001
0