peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 154

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

•
Figure 5-5
•
Figure 5-6
Valid C/BE combinations and the correspondence between local address, LBHE and the
mapping of PCI data to the local data bus are shown in table 5-2 and table 5-3. All
Data Sheet
LHOLD
LHLDA
Cycle
Bus
LCS1,2 (Out)
LCS0 (In)
LA(12:0)
LD(15:0)
LBHE
LRDY
Note 1: Supported in local bus master mode only.
Note 2: Ready controlled bus cycles only.
LWR
LRD
1
2
Intel Bus Mode
Intel Bus Arbitration
1
LHOLD remains asserted as long as a transaction is in
2
Read Cycle (16 Bit)
progress or while the latency timer is not expired
Address
read/write cycles as bus master
Read/Write Cycle
Data
154
One or more
Write Cycle (8 bit
Address
Interface Description
3
Data
1
)
PEB 3456 E
05.2001