peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 33

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
AE4
AC7
AE5
T2
Pin No.
DEVSEL
PERR
SERR
REQ
Symbol
Output (O)
Input (I)
s/t/s
s/t/s
o/d
t/s
33
Device Select
When activated by a slave, it indicates to
the current bus master that the slave has
decoded its address as the target of the
current transaction. If no bus slave
activates DEVSEL within six bus CLK
cycles, the master should abort the
transaction.
When the TE3-CHATT is bus master,
DEVSEL is input. If DEVSEL is not
activated within six clock cycles after an
address is output on AD(31:0), the TE3-
CHATT aborts the transaction.
When the TE3-CHATT is bus slave,
DEVSEL is output. DEVSEL is tri-stated,
when the TE3-CHATT is not involved in
the current transaction.
Parity Error
When activated, indicates a parity error
over the AD(31:0) and C/BE(3:0) signals
(compared to the PAR input). It has a
delay of two CLK cycles with respect to
AD and C/BE(3:0) (i.e., it is valid for the
cycle
corresponding PAR cycle).
PERR is asserted relative to the rising
edge of CLK.
System Error
The TE3-CHATT asserts this signal to
indicate an address parity error and report
a fatal system error.
SERR is an open drain output activated
on the rising edge of CLK.
Request
Used by the TE3-CHATT to request
control of the PCI bus. It is tri-state during
reset.
REQ is activated on the rising edge of
CLK.
immediately
Function
following
Pin Description
PEB 3456 E
05.2001
the