peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 246

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

GMASK
Global Interrupt Mask Register
Access
Address
Reset Value
Each bit in this register mask the interrupts, which are flagged in register GISTA/GIACK.
INTOF
LINT
IF
Q8..Q0
Data Sheet
INTOF
31
15
1
1
1
1
1
: read/write
: 0F4
: FFFFFFFF
Mask Interrupt Overflow
This bit masks the interrupt overflow interrupt.
Local Bus Interrupt
This bit masks bridging of interrupt from the local bus to the PCI bus.
0
1
Interrupt FIFO
This bit masks the internal mailbox/layer one interrupt FIFO.
0
1
Mask Interrupt Queue 8..0
Each of the bits Q8..Q0 masks an interrupt, which will be asserted, when
an interrupt vector has been written to the corresponding interrupt queue
8..0. Masking an interrupt does not suppress generation of the interrupt
vector itself.
0
1
1
1
H
Bridging of LINT to INTA enabled.
Bridging of LINT to INTA disabled.
IF interrupt is enabled.
IF interrupt is disabled.
Enable interrupt, when interrupt vector has been written to
selected interrupt queue.
Mask (Disable) interrupt, when interrupt vector has been written
to selected interrupt queue.
1
1
H
1
1
1
1
Q8
1
8
246
Q7
1
7
Q6
1
6
Q5
1
5
Q4
1
4
Register Description
Q3
1
3
Q2
1
2
PEB 3456 E
LINT
Q1
17
1
05.2001
Q0
16
IF
0