peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 399

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

•
Figure 9-12 Intel Bus Arbitration Timing
Table 9-9
Note: t
Data Sheet
60a
60b
61a
61b
62a
62b
63a
63b
67a
67b
68a
68b
69a
69b
No.
65
66
70
71
72
CYC
Parameter
LCLK to LA active delay
LCLK to LA float delay
LCLK to LCS2,1 active delay
LCLK to LCS2,1 float delay
LCLK to LBHE active delay
LCLK to LBHE float delay
LCLK to LRD, LWR active delay
LCLK to LRD, LWR float delay
LRDY low to LRD, LWR high delay
LRDY to LRD, LWR hold time
LD to LRD setup time
LD to LRD hold time
LD to LCLK setup time
LD to LCLK hold time
LCLK to LD delay
LCLK to LD float delay
LCLK to LHOLD delay
LHLDA asserted to Read/Write Cycle start
LHLDA minimum pulse width
is the clock period of the PCI clock.
Read/
LHOLD
LHLDA
Write
LCLK
Intel Bus Interface Timing (Master Mode)
70
71
399
72
min.
Limit Values
10
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
1
2
Electrical Characteristics
max.
10
10
10
10
10
10
10
10
10
10
10
PEB 3456 E
Unit
t
t
t
05.2001
CYC
CYC
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns