peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 93

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

PEB 3456 E
Functional Description
The CRC procedure is automatically invoked when the multiframe structure is enabled.
CRC errors in the received data stream are counted by the 16 bit CRC Error Counter
CEC (one error per submultiframe, maximum).
Additionally a CRC error interrupt vector with CRC set can be generated if enabled.
4.7.2.1
Synchronization Procedure of the Receiver
Multiframe alignment is assumed to have been lost if doubleframe alignment has been
lost (flagged at status bits FRS.LFA and FRS.LMFA). Either edge of these bits will cause
an LFA interrupt.
The multiframe resynchronization procedure starts when Doubleframe alignment has
been regained which is indicated by a FAS interrupt vector. For Doubleframe
synchronization refer to
Chapter
4.7.1. It may also be invoked by the user by setting bit
RFMR.FRS for complete doubleframe and multiframe resynchronization.
The CRC checking mechanism will be enabled after the first correct multiframe pattern
has been found. However, CRC errors will not be counted in asynchronous state.
The multiframe synchronous state is established after detecting two correct multiframe
alignment signals at an interval of n
2 ms (n = 1, 2, 3 …). The loss of multiframe
alignment flag FRS.LMFA will be reset. Additionally a multiframe alignment status
interrupt MFAS is generated on the falling edge of bit FRS.LMFA.
Automatic Force Resynchronization
In addition, a search for Doubleframe alignment is automatically initiated if two
multiframe pattern with a distance of n
2 ms have not been found within a time interval
of 8 ms after doubleframe alignment has been regained. The new search for frame
alignment will be started just after the previous frame alignment signal.
CRC-4 Interworking Mode
CRC-4 interworking is implemented according to ITU-T G.706 Appendix B. For
operational description refer to
Figure
4-11.
4.7.2.2
CRC-4 Performance Monitoring
In the synchronous state checking of multiframe pattern is disabled. However, with bit
RFMR.ALMF an automatic multiframe resynchronization mode can be activated. If 915
out of 1000 errored CRC submultiframes are found then a false frame alignment will be
assumed and a search for double- and multiframe pattern is initiated. The new search
for frame alignment will be started just after the previous basic frame alignment signal.
The internal CRC-4 resynchronization counter will be reset when the multiframe
synchronization has been regained.
Data Sheet
93
05.2001