peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 96

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

4.7.2.4
Due to signaling procedures using the five S
CRC-4 multiframe structure, two possibilities of access via the microprocessor are
implemented.
• The standard procedure, allows reading/writing the S
• The extended access via the receive and transmit FIFOs of the signaling controller. In
S
Four consecutive received S
combinations. The TE3-CHATT can be programmed to detect any bit combination on
one S
register RCR2.SASSM. A valid S
corresponding status in register RSAW4 will be set. Register RSAW4 is from type “Clear
on Read”. With any change of state of the selected S
Valid’ interrupt vector will be generated.
During the basic frame asynchronous state updating of register RSAW4 and interrupt
vector generation is disabled. In CRC-4 multiframe format the detection of the S
combinations can be done either synchronous or asynchronous to the submultiframe. In
synchronous detection mode updating of register RSAW4 is done in the multiframe
synch. state. In asynchronous detection mode updating is independent to the multiframe
synchronous state.
S
The S
sequence 0001
in every submultiframe on a selectable S
CRC errors are reported from the TE via S
multiframe synchronous state.
Data Sheet
a
a
-bit Detection according to ETS 300233
-bit Error Indication Counters
and XSAW1 through XSAW3.
Registers RSAW1-3 contains the service word information of the previously received
CRC-4 multiframe or 8 doubleframes (bit slots 4-8 of every service word). These
registers will be updated on every multiframe. Optionally TE3-CHATT provides the
possibility to check the received S
vector is generated on S
With the transmit multiframe begin the contents of this registers XSAW1-3 will be
copied into shadow registers. The contents will subsequently sent out in the service
words of the next outgoing CRC-4 multiframe (or doubleframes). The TXSA interrupt
request that these registers should be serviced. If requests for new information will be
ignored, current contents will be repeated.
this mode it is possible to transmit / receive a HDLC frame or a transparent bit stream
in any combination of the S
a
a
-bit out of S
-bit error indication counter CRC1 (16 bits) counts either the received bit
S
a
-bit Access
B
and 0011
a4
through S
B
a
-data change in order to reduce microprocessor bus load.
or two user programmable values defined in register VCRC
a
a
-bits are checked on the by ETS 300233 defined S
-bits.
a8
. Enabling of specific bit combination can be done via
a
-bit combination must occur three times in a row. The
a
-data with the S
a
-bit. In the primary rate access digital section
96
a
-bits (S
a6
. Incrementing is only possible in the
a4
a
-data received earlier. An interrupt
… S
a
a
-bit registers RSAW1 to RSAW3
-bit combinations a ’SSM Data
a8
) of every other frame of the
Functional Description
PEB 3456 E
05.2001
a
a
-bit
-bit