peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 161

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

5.5
A test access port (TAP) is implemented in the TE3-CHATT. The essential part of the
TAP is a finite state machine (16 states) controlling the different operational modes of
the boundary scan. Both, TAP controller and boundary scan, meet the requirements
given by the JTAG standard: IEEE 1149.1. Figure 5-11 gives an overview about the TAP
controller.
•
Figure 5-11 Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan operation is planned TRST has to be connected with V
TDI do not need to be connected since pull- up transistors ensure high input levels in this
case. Nevertheless it would be a good practice to put the unused inputs to defined levels.
In this case, if the JTAG is not used:
TMS = TCK = ‘1’ is recommended.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i. e. TRST is connected to V
unconnected due to its internal pull up. Test data at TDI are loaded with a clock signal
connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state to
another; constant ‘1’ on TMS leads to normal operation of the chip.
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells
(data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note
that most functional output and input pins of the TE3-CHATT are tested as I/O pins in
boundary scan, hence using three cells. The boundary scan unit of the TE3-CHATT
Data Sheet
JTAG Interface
TCK
TRST
TMS
TDI
TDO
CLOCK
Reset
Test
Control
Data in
Enable
Data out
Test Access Port (TAP)
- Finite State Machine
- Instruction Register (4 bit)
- Test Signal Generator
Clock Generation
TAP Controller
CLOCK
161
ID Data out
Control
Bus
SS Data
out
Interface Description
DD3
2
1
n
PEB 3456 E
Pins
or it remains
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SS
. TMS and
05.2001