peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 108

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

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Figure 4-13 Interrupt Driven Transmit Sequence Example
Note: Transmit FIFO is 16 bit wide. In the given example writing 32 bytes requires 16
4.9
The M12 multiplexer and the DS2 framer can be operated in two modes:
• M12 multiplex format according to ANSI T1.107
• ITU-T G.747 format
4.9.1
The framing structure of the M12 signal is shown in Table 4-11. A DS2 multiframe
consists of four subframes. Each subframe combines 6 blocks with 49 bits each. The first
bit of each block contains an overhead (OH) bit and 48 information bits. The 48
information bits are divided into four time slots of 12 bits each. The first time slot is
Data Sheet
FDL channel
Local Bus
Interface
write accesses. Writing 15 byte requires 8 accesses.
M12 Multiplexer/Demultiplexer and DS2 framer
M12 multiplex format
Transmit frame (79 bytes)
32 bytes
WR
XTF
XPR
32 bytes
32 bytes
WR
XTF
108
XPR
32 bytes
15 bytes
WR
Functional Description
XTF+XME
15 bytes
PEB 3456 E
XPR
ALLS
05.2001