peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 24

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

1.1.3
• Frame alignment/synthesis for 1544 kbit/s according to ITU-T G.704
• Supports T1 frame alignment for F4, SF (F12) and ESF (F24) mode
• Error checking via CRC-6 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC, framing errors, loss of frame alignment,
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm)
• Detection of LOS (Red Alarm)
• Pseudo-random bit sequence generator and monitor for one logical channel
• Programmable in-band loop code detection/generation according to TR 62411
1.1.4
• FDL-channel protocol for ESF format according to ANSI T1.403 specification or
• Supports HDLC mode with address recognition
• Supports BOM mode
• FIFO Buffers (64 bytes deep) for efficient transfer of data packets
1.1.5
• Frame alignment/synthesis for 2048 kbit/s according to ITU-T G.704
• Programmable formats: Doubleframe, CRC-4 Multiframe
• CRC-4 to Non-CRC-4 Interworking of ITU-T G.706 Annex B
• Error checking via CRC-4 procedures according to ITU-T G.706
• Performance monitor: 16 bit counter for CRC-, framing errors, error monitoring via E-
• Insertion and extraction of alarms (AIS, Remote (Yellow) Alarm, ...)
• Pseudo-random bit sequence (PRBS) generator and monitor for one logical channel
• Programmable in-band loop code detection / generation according to TR 62411
1.1.6
• HDLC controller with address recognition and programmable preamble
• Time slot 0 S
• HDLC access to any S
• FIFO Buffers (64 byte deep) for efficient transfer of data packets
1.1.7
• User specified PRBS/Fixed Pattern with programmable length of 1 to 32 bits
• Optional Bit Inversion
Data Sheet
loss of signal AIS
according to ITU-T O.151
according to AT&T TR54016
Selectable conditions for recover / loss of frame alignment
bit and S
Frame Alignment T1 Features
Signaling Controller T1 Features
Frame Alignment E1 Features
Signaling Controller E1 Features
Bit Error Rate Tester
a6
bit
a8-4
HDLC handling via FIFOs
a
-bit combination
24
TE3-CHATT Overview
PEB 3456 E
05.2001