peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 59

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

4.3
Each packet or part of a packet is referenced by a descriptor. The descriptors form a link
list, thus connecting all packets together. Packet data as well as descriptors are located
in system memory. Both the TE3-CHATT and the system CPU operate on these data
structures.
Each logical channel has its dedicated linked list of descriptors, one for receive direction
and one for transmit direction. This type of data structure allows channel specific
memory organization which can be specified by the system processor. It provides an
optimized way to transfer data packets between the system processor and the TE3-
CHATT.
The TE3-CHATT has a flexible DMA controller to transfer data either from the internal
receive buffer to the shared memory (receive direction) or from the shared memory to
the internal transmit buffer (transmit direction). Each DMA works on one linked list. Each
linked list located in system memory is associated with one of the 256 transmit channels
or one of 256 receive channels.
The address generator of the DMA controller supports full link list handling. Descriptors
are stored independently from the data buffers, thus allowing full scatter/gather
assembly and disassembly of data packets.
4.3.1
A descriptor is used to build a linked list, where each member of the linked list points to
a data section. A descriptor consists of four DWORDS
containing link and packet information, are provided by the system CPU and the last
DWORD contains status information, which is written when the TE3-CHATT has finished
operation on a descriptor.
The data section itself can be of any size up to the maximum size of 65535 bytes per
descriptor and is defined in the first DWORD of a descriptor. Each logical data packet
can be split into one or multiple parts, where each part is referenced by one descriptor,
and all parts are referenced by a linked list of descriptors. The descriptor containing the
last part of a data packet is marked with a frame end bit. The descriptor following the
marked descriptor therefore contains the beginning of the next data packet (Figure 4-6).
The last descriptor in a linked list is marked with a hold indication.
For ease of programming the transmit descriptor and the receive descriptor are
structured the same way, thus allowing to link a receive descriptor directly into the linked
list of the transmit queues with minimum descriptor processing.
1)
Data Sheet
Data Management Unit
Descriptor Concept
59
1)
. The first three DWORDS,
Functional Description
PEB 3456 E
05.2001