peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 103

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

4.8.2
In transparent mode, fully transparent data transmission/reception without HDLC
framing is performed, i.e. without FLAG generation/recognition, CRC generation/check,
or bit-stuffing. This feature can be profitably used e.g for:
• Specific protocol variations
• Test purposes
Data transmission is always performed out of the transmit FIFO (XFF.XFIFO). In
transparent mode receive data is shifted into the receive FIFO without protocol
processing.
If the transparent mode is selected, the TE3-CHATT supports the continuous
transmission of the contents of the transmit FIFO.
After having written 1 to 32 bytes to transmit FIFO, the command HND via the CMDR
register forces the TE3-CHATT to repeatedly transmit the data stored in transmit FIFO
to the remote end.
The cyclic transmission continues until a reset command (HND. SRES) is issued or with
resetting CMDR.XREP, after which continuous ‘1’-s are transmitted.
4.8.3
The signalling controller supports the DL channel protocol for ESF format according to
ANSI T1.403 or according to AT&T TR54016. The Bit Oriented Message (BOM) receiver
can be switched on or off separately. If the signalling controller is used for HDLC formats
only, the BOM receiver has to be switched off (RCR1.BRAC = ’0’). If HDLC and BOM
receiver are switched on, an automatic switching between HDLC and BOM mode is
done, which depends on the received bit sequence ( 01111110
or more consecutive ones are detected, the BOM mode is entered automatically. Upon
detection of a flag in the data stream, the FDL-Macro switches back to HDLC-mode.
Once in BOM mode, if eight consecutive ones are not detected in 32 bits, a BOM header
error will be declared.
Transmission of BOM data is done via the transparent mode of the signalling controller.
BOM Regular Mode
The following byte format is assumed (the left most bit is received first):
111111110xxxxxx0
The signalling controller uses the FF
the receive FIFO (first bit received: LSB) if it starts and ends with a ‘0’. Bytes starting or
ending with a ‘1’ are not stored. If there are no 8 consecutive one’s detected within 32
bits and the FDL-Macro is currently in the BOM mode, an ’Incorrect Synchronization
Format’ interrupt vector is generated. However, byte sampling is not stopped.
Data Sheet
Transparent Mode
BOM Mode
B
H
byte for synchronization, the next byte is stored in
103
Functional Description
B
or 11111111
PEB 3456 E
B
). If eight
05.2001