peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 124

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

•
Figure 4-17 Layer Two Interrupts (Channel, command, port and system
As soon as the interrupt controller has written an interrupt vector to one of the nine
interrupt queues the PCI interrupt pin INTA is asserted. The global interrupt status
register indicates in which interrupt queue the interrupt vector can be found. Each of the
Data Sheet
FFFFFFFF
00000000
IQBA
H
H
Interrupt status:
GISTA, GMASK
Interrupt queue setup:
IQIA, IQBA, IQL, IQMASK
System memory
Interrupt queue
interrupts
Int. vector setup:
CONF1, CONF2
interrupts
System
1
interface
2
PCI
IV
controller
Int. vector setup:
CSPEC_IVMASK,
CSPEC_BUFFER
Interrupt
Command
interrupts
Channel,
5
124
1. Interrupt source forwards interrupt vector to
2. Interrupt controller moves interrupt vector to
3. Interrupt controller asserts INTA (if enabled).
4. Microprocessor reads status register GISTA.
5. Microprocessor reads interrupt queue.
interrupt controller.
interrupt queue.
Interrupt bus
3
1
INTA
256
Microprocessor
Int. vector setup:
PMR, CONF2
4
interrupts
Functional Description
Port
from layer one
interrupt FIFO
PCI bus
PEB 3456 E
05.2001
LINT