peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 89

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

• Errored block counter: This counter will be incremented, if a multiframe has been
Clearing and updating of the counters is done according to bit RFMR1.ECM. If this bit is
reset, the error counter is permanently updated. Reading of actual error counter status
is always possible. The error counters are reset by reading the corresponding status
register. If RFMR1.ECM is set, every second the error counter will be latched and then
automatically reset. The latched error counter state should be read within the next
second.
4.6.4.6
A Pseudo-random bit sequence (PRBS) generator and monitor according to ITU O.151
can be activated for one particular logical channel. The PRBS pattern type can be
selected as 2
which should be used for PRBS can be defined in R/TPTSL register.
Additionally a fixed pattern can be programmed via registers R/TFPR0 and R/TFPR1
with length up to 32 bit to be defined in R/TPRBSC.FPL.
The PRBS monitor searches synchronization on the inverted and non-inverted PRBS
pattern. The current synchronization status is reported in status and interrupt status
registers. Each PRBS bit error will increment an error counter. An additional counter will
accumulate the total number of received bits. Synchronization will be reached within 400
ms with a probability of 99.9% and a BER of 1/10.
4.7
The operating mode of the TE3-CHATT is selected by programming the carrier data rate
and characteristics, multiframe structure, and signaling scheme.
The TE3-CHATT implements the standard framing structures for E1 or PCM 30 (CEPT,
2048 Kbit/s) carriers. The internal HDLC controller supports signaling procedures like
signaling frame synchronization/synthesis and signaling alarm detection in all framing
formats.
Summary of E1- Framing Modes:
• Doubleframe format according to ITU-T G. 704.
• Multiframe format according to ITU-T G. 704
• Multiframe format with CRC-4 to non CRC-4 interworking according to ITU-T G. 706.
After reset, the TE3-CHATT is switched into doubleframe format automatically.
Switching between the framing formats is done via bit T/RFMR.FM
Data Sheet
received with framing errors or CRC errors (ESF only).
CRC-4 processing according to ITU-T G. 706.
Pseudo-random Bit Sequence Generator and Monitor
E1 Framing and Signaling
15
-1 or 2
20
-1 via R/TPRBSC.PRP. Moreover, the number of the time slots
89
Functional Description
PEB 3456 E
05.2001