peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 208

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

CSPEC_BUFFER
Channel Specification Buffer Configuration Register
Access
Address
Reset Value
TQUEUE
ITBS
TBRTC
Data Sheet
31
15
TQUEUE(2:0)
TBFTC(3:0)
29
: read/write
: 020
: 00200000
Transmit Interrupt Vector Queue
This bit field determines the interrupt queue where channel interrupts
transmit will be stored.
Individual transmit buffer size
Note: Please note that the internal architecture is 32 bit wide. Therefore
The transmit buffer size configures the number of internal transmit buffer
Note: The sum of transmit forward threshold and transmit refill
Transmit Buffer Refill Threshold Code
Note: Please note that the internal architecture is 32 bit wide. Therefore
TBRTC is a coding for the transmit refill threshold. Please refer to Table
8-7 for correspondence between code and threshold.
The internal transmit buffer has a programmable number of buffer
locations per channel. When the number of free locations reaches the
transmit buffer refill threshold the internal transmit buffer requests new
data from the data management unit.
28
12
H
locations for a particular channel. Buffer locations will be
allocated on command transmit init and released after command
transmit off.
each buffer location corresponds to four data octets.
threshold must be smaller than the internal buffer size.
each buffer location corresponds to four data octets.
11
H
TBRTC(3:0)
8
208
0
ITBS(12:0)
6
RQUEUE(2:0)
4
Register Description
3
RBTC(3:0)
PEB 3456 E
05.2001
16
0