peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 169
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 169 of 424
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7
Since the term “initialization” can have different meanings, the following definition
applies:
Chip Initialization
Generating defined values in all on-chip registers, RAMs (if required), flip-flops etc.
Mode Initialization
Software procedure, that prepares the device to its required operation, i.e. mainly writing
on-chip registers to prepare the device for operation in the respective system
environment.
Operational programming
Software procedures that setup, maintain and shut down operational modes, i.e. initialize
logical channel or maintain framing operations on selected ports.
7.1
Hardware reset
The hardware reset RST has to be applied to the device. Chip input TRST must be
activated prior to or while asserting RST and should be held asserted as long as the
boundary scan operation is not required. System clock must start running during reset.
During reset:
• All I/Os and all outputs are tri-state.
• All registers, state machines, flip-flops etc. are set asynchronously to their reset
• All interrupts are masked.
• The register bit CONF1.STOP is set to ‘1’.
After hardware reset (RST deasserted) system clock CLK is assumed to be running.
Serial clocks must be low/high or running. The PCI and the local bus interface pins go
into their idle state. All serial line outputs are tri-state.
The PCI interface becomes active and depending on input pin SPLOAD starts to read
subsystem ID/subsystem vendor ID and Memory commands out of external EEPROM
via the SPI interface. The serial clock is derived from the PCI clock. As long as this
procedure is active, the PCI interface answers all accesses with retry. After the PCI
interface has finished its self initialization it can be configured with PCI configuration
cycles.
In parallel to PCI self initialization the internal modules start their RAM initialization. As
long as the RAM initialization is running the internal modules indicate this condition with
Data Sheet
values and all internal modules are set to their initial state.
Reset and Initialization procedure
Chip Initialization
169
Reset and Initialization procedure
PEB 3456 E
05.2001
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