peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 216

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

MFLE
MFL
MBIM
PBIM
RBIM
RFIM
Data Sheet
IIP will be asserted. When IIP is deasserted system software can reset
SRST to ’0’ to start normal operation again.
0
1
Maximum Frame Length Check Enable
0
1
Maximum Frame Length
MFL defines the maximum length of incoming data packets. Packets
exceeding the specified length are reported in the status field of the
receive descriptor and if selected in an additional channel interrupt.
Mailbox Interrupt Vector Mask
This bit enables or disables mailbox system interrupt vectors generated
by the mailbox.
0
1
PCI Bridge Interrupt Vector Mask
This bit enables or disables the ’PCI Access Error’ interrupt vector
generated by the PCI bridge.
0
1
Receive Buffer Interrupt Vector Mask
This bit enables or disables system interrupt vectors ’Receive Buffer
Queue Early Warning’ and ’Receive Buffer Action Queue Early Warning’
which are generated by the receive buffer. RBIM is valid only if bit RBM
is set.
0
1
Receive Buffer Failed Interrupt Vector Mask
This bit enables or disables the ’Receive Buffer Access Failed’ interrupt
vector.
0
1
Normal operation
Start software reset.
Disable maximum frame length check.
Enable maximum frame length check.
Enable interrupt vector.
Disable interrupt vector.
Enable interrupt vector.
Disable interrupt vector.
Enable interrupt vector.
Disable interrupt vector.
Enable interrupt vector.
Disable interrupt vector.
216
Register Description
PEB 3456 E
05.2001