peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 298

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

D2RCFG
DS2 Receive Configuration Register
Access
Address
Reset Value
Note: ITU-T G.747 mapping and loopback codes are controlled by bits E1 and LPC in
E1/T1 and loopback codes are controlled by E1 and LPC fields of the D2TCFG register.
ECM
MFM
FFM
Data Sheet
15
0
the DS3 transmit configuration register D2TCFG.
0
0
: read/write
: 224
: 0000
Error Counter Mode
DS2 errors are counted in background and copied to foreground (error
counter registers) when condition selected via ECM is met.
0
1
Multiframe Framing Mode
This bit selects the M-bit error condition which triggers the DS2 framer to
start a new frame search. It is valid in DS1 mode only.
0
1
F-Framing Mode
This bit selects the F-bit error condition which triggers the DS2 framer to
start a new frame search.
0
1
0
H
H
(PCI), 92
Counter values are copied to foreground when copy command is
executed. See also register DS3COM.
The counter values are copied to the foreground register in one
second intervals. At the same time the background registers are
reset to zero. This operation is synchronous with the periodic one
second interrupt which alerts software to read the register.
F-frame search started if 3 contiguous multiframes have M-bit
errors.
Inhibit new F-frame search due to M-bit errors.
A new frame search is started when 2 out of 4 contiguous F-bits
are in error.
A new frame search is started when 2 out of 5 contiguous F-bits
are in error.
0
0
H
(Local bus)
0
0
298
0
0
0
0
Register Description
ECM
3
0
PEB 3456 E
MFM FFM
1
05.2001
0