peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 49

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

• The configuration busses, which serve as the standard programming interface to
• The interrupt busses, which collect all interrupt information and forward them to the
The chip’s core functions are all operated with the PCI clock. Transfers between clocking
regions (serial clocks and system clock) are implemented only in the serial interface.
3.4
The following section gives a brief overview to the function of each block. For a detailed
description of each function refer to
T1/E1 Interface/Unchannelized Interface
The T1/E1 interface consists of the subfunctions receive and transmit. This block
provides the function of serial/parallel and parallel/serial conversion for up to 28
incoming and up to 28 outgoing tributaries of the DS3 signal. Serial data is transferred
between the internal clocking system, which is derived from the PCI clock, and the
various line clocks. This provides a unique clocking scheme on the internal interfaces.
The aggregate bandwidth of all enabled tributaries can be up to 45 Mbit/s in each
direction.
Time slot assigner
The time slot assigner exchanges data with the serial interface on a 8 bit parallel bus,
thus funneling all data of up to 28 interfaces. The time slot assigner provides freely
programmable mapping of any time slot or any combination of time slots to 256 logical
channels. A programmable mask can be provided to allow subchanneling of the
available time slots which allows channel data rates starting at 8kbit/s.
At the protocol machine interface the time slot assigner and the protocol machine
exchanges channel oriented data (8 bit) together with the time slots masks.
Protocol handler
Two protocol machines, one for receive direction and one for transmit direction, provide
protocol handling for up to 256 logical channels and a maximum serial aggregate data
rate of up to 45 Mbit/s per direction. The protocol machines implement four modes, which
can be programmed independently for each logical channel: HDLC, bit-synchronous
PPP, octet-synchronous PPP and Transparent Mode A, including frame synchronous
TMA.
Data Sheet
access the chip internal registers and functions either via PCI bus or via the local bus
interface.
corresponding interrupt handler.
Block Description
“Functional Description” on Page
49
General Overview
53.
PEB 3456 E
05.2001