peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 117

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

CP
P
X
[84]
4.10.2.1 Synchronization Procedure
The integrated DS3 framer searches for the frame alignment pattern ’1001’ and when
found for the multiframe alignment pattern in each of the seven DS3 subframes. Frame
alignment is declared when the multiframe alignment pattern is found in three
consecutive DS3 frames. The P-bits and the X-bits are ignored during synchronization.
Loss of frame is declared, when 3 out of 8 or 3 out of 16 incorrect F-bits are found or
when one or more incorrect M-bits are found in 3 out of 4 subframes.
4.10.2.2 Multiplexer/Demultiplexer
Demultiplexer
The demultiplexer extracts seven DS2 signals from the incoming DS3 signal. Since the
DS3 signal is always stuffed the stuffing bit assigned to each DS2 signal is discarded.
Multiplexer
The multiplexer combines seven DS2 signals to form a DS3 signal and automatically
inserts a stuffing bit for each DS2 signal.
4.10.2.3 X-bit
The TE3-CHATT provides access to the X-bits via internal registers.
Data Sheet
monitor the performance of a DS3 signal. Upon detection of either error in the incoming data
stream the FEBE-bits are set automatically to ’000’ in the outgoing direction. Received far end
block errors are counted.
The CP-bits are used to carry path parity information and are set to the same value as the P-bits.
In receive direction the CP-bits are checked against the calculated parity and differences are
counted.
The P-bits contain parity information and are automatically calculated as even parity on all
information bits of the previous DS3 frame.
The X-bits are used for transmission of asynchronous in-service messages. Both X-bits must be
identical and may not change more than once every second. Access to the X-bits is possible via
a register.
These bits represent a data block, which consists of 84 bits. [84] consists of seven time slots with
12 bits each and they are assigned to one of the seven participating DS2 signals.
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Functional Description
PEB 3456 E
05.2001