peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 171

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

8
The register description of the TE3-CHATT is divided into two parts, an overview of all
internal registers and in the second part a detailed description of all internal registers.
8.1
The first part of the register overview describes the PCI configuration space registers.
The second part describes the register set which can be accessed from PCI side only.
These registers are used to setup the main operation modes and to run the channel
engines of the device. The last part describes the register set of the framing engines, the
signalling controller, the mailbox and the local interrupt FIFO. These registers may be
accessed through the local microprocessor interface or via PCI.
Note: Register locations not contained in the following register tables are “reserved”. In
8.1.1
Table 8-1
Register
Standard configuration space register
DID/VID
STA/CMD
CC/RID
BIST/
HEAD/
LATIM/
CLSIZ
BAR1
BAR2
BARX
Data Sheet
general all write accesses to reserved registers are discarded and read access to
reserved registers result in 00000000
system software shall access documented registers only, since writes to reserved
registers may result in unexpected behavior. The read value of reserved registers
shall be handled as don’t care.
Unused and reserved bits are marked with a gray box. The same rules as given
for register accesses apply to reserved bits, except that system software shall
write the documented default value in reserved bit locations.
Register Description
Register Overview
PCI Configuration Register Set (Direct Access)
PCI Configuration Register Set
Access Address
R/W
R/W
R/W
R/W
R
R
R
14
0C
00
04
08
10
14
H
-24
H
H
H
H
H
H
H
2108110A
02A00000
02800001
00000000
00000000
00000000
00000000
Reset
value
171
H
. Nevertheless, to allow future extensions,
H
H
H
H
H
H
H
Comment
Device ID/Vendor ID
Status/Command
Class Code/Revision ID
Built-in Self Test/
Header Type/
Latency Timer/
Cache Line Size
Base Address 1
Base Address 2
Base Address Not Used
Register Description
PEB 3456 E
05.2001
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