peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 243

• Manufacturer Part Number: peb3456e
• Description: Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
• Manufacturer: Infineon Technologies Corporation

IQMASK
Interrupt Queue High Priority Mask
Access
Address
Reset Value
For a description of the interrupt concept and interrupt vectors see
In normal operation each channel interrupt vector is written to the interrupt queue
associated with a specific channel, that is interrupt queue 0 to 7. The interrupt queue
mask provides the functionality to forward selected channel interrupts to the high priority
interrupt queue, which is hardwired as queue 7.Therefore a mask can be set for each of
the interrupt queues, which specifies the channel interrupt vector to be forwarded to the
high priority interrupt queue. To set the IQMASK for interrupt queues 0 to 6, system
software must first program IQMASK. Afterwards the mask is released by selecting the
affected interrupt queue via bit field IQIA.Q and setting of bit SIQM.
Those interrupt vectors which have an interrupt bit set, that is also masked in this high
priority mask are forwarded to the high priority interrupt queue instead of the regular
interrupt queue associated with a specific channel.
If a channel interrupt vector has at least one interrupt bit set, that is also masked in the
high priority mask, the interrupt vector will be forwarded to the high priority interrupt
queue.
In case that a channel interrupt vector has at least one bit set, that is not masked in the
high priority mask, the interrupt vector is queued into the regular interrupt queue
associated with the corresponding channel.
Data Sheet
RHI
THI
31
15
RAB RFE HRAB MFL RF0D CRC ILEN RFOP SF
TAB
30
14
13
0
: read/write
: 0EC
: 00000000
HTAB
28
12
H
11
0
H
10
0
0
9
0
8
243
UR
23
7
TFE
22
6
IFTC
0
5
0
0
Register Description
SFD
Chapter
0
3
SD
0
2
PEB 3456 E
4.13.1.
0
0
05.2001
16
0
0
0