dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 99

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 119. Lane 3 configuration registers (address 10h to 1Dh) bit description
Default settings are shown highlighted.
Table 120. LN32_SELECT register (address 1Eh) bit description
Default settings are shown highlighted.
Table 121. PAGE_ADDRESS register (address 1Fh) bit description
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
1Ah
1Bh
1Ch
1Dh
Bit
7 to 0
Bit
4 to 0
Symbol
LN32_SEL
Symbol
PAGE[4:0]
Register
LN3_CFG_10
LN3_CFG_11
LN3_CFG_12
LN3_CFG_13
Bit
7
4 to 0
7 to 0
7 to 0
7 to 0
Symbol
LN3_HD
LN3_CF[4:0]
LN3_RES1[7:0]
LN3_RES2[7:0]
LN3_FCHK[7:0]
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
W
Access
R/W
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
0
1
Value
0h
Description
Description
page_address
specifies the lane affected by DLP_STROBE
Access Value
R
R
R
R
lane 2
lane 3
-
-
-
-
-
…continued
DAC1628D1G25
Description
high density
number of control words per
frame cycle
lane 3 reserved field
lane 3 reserved field
lane 3 checksum
© NXP B.V. 2011. All rights reserved.
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