dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 121

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 156. HS_RX monitor registers (address 19h to 1Ch) bit description
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
1Ah
1Bh
1Ch
Register
HS_RX_1_MON
HS_RX_2_MON
HS_RX_3_MON
Bit
3
2
1
0
3
2
1
0
3
2
1
0
Symbol
HS_RX_1_EQ_TST_
DTY_OUT
HS_RX_1_EQ_OFS_POL
HS_RX_1_LOCK_REF_
CLK
HS_RX_1_CDR_FACQ_
BUSY
HS_RX_2_EQ_TST_
DTY_OUT
HS_RX_1_EQ_OFS_POL
HS_RX_2_LOCK_REF_
CLK
HS_RX_2_CDR_FACQ_
BUSY
HS_RX_3_EQ_TST_DTY_
OUT
HS_RX_3_EQ_OFS_POL
HS_RX_3_LOCK_REF_
CLK
HS_RX_3_CDR_FACQ_
BUSY
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access
R
R
R
R
R
R
R
R
R
R
R
R
Value
0
1
0
1
-
0
1
0
1
-
0
1
0
1
-
…continued
Description
actual state
hs_rx_1_eq_test_duty_out
hs_rx_ln1 equalizer offset
hs_rx_1 lock to reference clock
actual state
hs_rx_1_eq_test_duty_out (not
used)
actual state
hs_rx_2_eq_test_duty_out
hs_rx_ln2 equalizer offset
hs_rx_2 lock to reference clock
actual state
hs_rx_2_eq_test_duty_out (not
used)
actual state
hs_rx_3_eq_test_duty_out
hs_rx_ln3 equalizer offset
hs_rx_3 lock to reference clock
actual state
hs_rx_3_eq_test_duty_out (not
used)
DAC1628D1G25
negative
positive
not locked to reference clock
(pfd mode)
locked to reference clock
(pfd mode)
negative
positive
not locked to reference clock
(pfd mode)
locked to reference clock
(pfd mode)
negative
positive
not locked to reference clock
(pfd mode)
locked to reference clock
(pfd mode)
© NXP B.V. 2011. All rights reserved.
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