dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 98

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 118. Lane 3/lane 2 sample LSB/MSB registers (address 0Eh to 0Fh) bit description
Default settings are shown highlighted.
Table 119. Lane 3 configuration registers (address 10h to 1Dh) bit description
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
0Eh
0Fh
Address
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
Register
LN32_SAMPLE_LSB
LN32_SAMPLE[15:8]
Register
LN3_CFG_0
LN3_CFG_1
LN3_CFG_2
LN3_CFG_3
LN3_CFG_4
LN3_CFG_5
LN3_CFG_6
LN3_CFG_7
LN3_CFG_8
LN3_CFG_9
Bit
7 to 0
7 to 4
3 to 0
6
5
4 to 0
7
4 to 0
7 to 0
4 to 0
7 to 0
7 to 6
4 to 0
7 to 5
4 to 0
7 to 5
4 to 0
Bit
7 to 0
7 to 0
Symbol
LN3_DID[7:0]
LN3_ADJCNT[3:0]
LN3_BID[3:0]
LN3_ADJDIR
LN3_PHADJ
LN3_LID[4:0]
LN3_SCR
LN3_L[4:0]
LN3_F[7:0]
LN3_K[4:0]
LN3_M[7:0]
LN3_CS[1:0]
LN3_N[4:0]
LN3_SUBCLASSV[2:0]
LN3_N’[4:0]
LN3_JESDV
LN3_S[4:0]
All information provided in this document is subject to legal disclaimers.
Symbol
LN32_SAMPLE[7:0]
LN32_SAMPLE[15:8] R
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value
R
Access Value
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
00
01
10
-
-
000
001
-
DAC1628D1G25
Description
internal DLP data on lane 2 or
lane 3 depending on the value of
LN10_SELECT (bit 1E; LSB)
The data are strobed by
DLP_STROBE (see
1D).
internal DLP data on lane 2 or
lane 3 depending on the value of
LN10_SELECT (bit 1E; MSB)
The data are strobed by
DLP_STROBE (see
1D).
Description
lane 3 device ID
lane 3 adjustable counter
lane 3 bank ID
lane 3 adjustable direction
lane 3 adjustable phase
lane 3 lane ID
scrambling on
number of lanes minus 1
number of octets per frame
minus 1
number of frames per
multi-frame minus 1
number of converters per
device minus 1
number of control bits
converter resolution minus 1
lane 3 JSED204B subclass
version
number of bits per sample
minus 1
Lane 3 JESD204 version
number of samples per
converter per frame cycle
minus 1
subclass 0
subclass 1
subclass 2
version A
version B
© NXP B.V. 2011. All rights reserved.
Table
Table
89, bit
89, bit
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