dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 48

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 31.
Default values are shown highlighted.
Table 32.
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
7
6
5
4 to 3
2 to 1
0
Bit
7
6
4
3
2 to 0
Symbol
PLL_BYP
CLK_DET_PON
RESERVED
PLL_DIV[1:0]
PLL_PH_SEL
PLL_PON
Symbol
DCLK_MON_RST
DCLK_MON
WCLK_PON
WCLK_DIV_BYP
WCLK_DIV_SEL[2:0]
10.17.2.2 Page x01 bit definition detailed description
PLLCFG register (address 02h) bit description
WCLKGENCFG register (address 04h) bit description
The tables in this section contain detailed descriptions of the page x01 registers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R
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Value
0
1
0
1
-
00
01
10
11
00
01
10
11
0
1
Rev. 1.1 — 10 October 2011
Value
0
1
0
1
0
1
0
1
000
001
010
011
100
110
111
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
DAC clock generated by PLL
DAC clock provided via clock-in (bypass mode)
PLL_PON must be powered-down when PLL_Bypass is
enabled.
PLL input clock detection disabled (power-down)
PLL input clock detection enabled
reserved
DAC at 2  dclk
DAC at 4  dclk
DAC at 8  dclk
undefined
DAC clock phase shift = 0
DAC clock phase shift = 120
DAC clock phase shift = 240
DAC clock phase shift = 240
PLL oscillator output disabled (power-down)
PLL oscillator output enabled.
PLL_BYP must be disabled when PLL_PON is enabled
Description
no action
reset dclk_mon_flag
dclk_mon OK
dclk_mon failure
wclk disabled (power-down)
wclk enabled
wclk depends on wclk_div_sel
wclk = DAC clock
wclk = DAC clock / 2
wclk = DAC clock / 3
wclk = DAC clock / 4
wclk = DAC clock / 6
wclk = DAC clock / 12
wclk = DAC clock / 16
wclk = DAC clock / 24
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
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