dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 35

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
Fig 22. SPI register pages repartition
Fig 23. Page x00, interface DAC DSP overview
PAGE x00: INTERFACE DAC DSP
two’s complement
SPI_RST
INPUT DATA
3W_SPI
binary offset
FORMAT
CODING:
SPI
PAGE x08/x09: JESD204 READ CONFIGURATION
DID, BID, ADJCNT, ADJDIR, PHADJ, SCR, L,
F, K, M, N, N, SubclassV, S, HD, CF,
JESDVersion, RES1, RES2, FCHK
PAGE x10: RX PHY
PAGE x11:
RX PHY MONITORING
Auto Equalizer
CDR
Termination
Calibration
PAGE x0A: MAIN CONTROLS
SYNC_OUTN
VIN_P0
VIN_N0
VIN_P1
VIN_N1
VIN_P2
VIN_N2
VIN_P3
VIN_N3
SYNC_OUTP
10.17.1 Page x00: Interface DAC DSP
10.17
EQUALIZER
AUTO CAL
CONTROL
~1 (sample repetition)
INTERPOLATION
POWER ON
INTERPOLATION:
GAP_PON
IC_PON
L0
L1
L2
L3
FILTERS
x2
x2
x4
x8
Registers
Figure 22
This page specifies the main features of the digital signal processing of the
DAC1628D1G25.
Eq
Eq
Eq
Eq
PAGE x03: RX DLP
PAGE x04:
RX DLP MONITORING
Lanes Lock
ILA monitoring
Error detection
Simple BER
Flags counter
MODULATION (NCO)
SINGLE SIDE BAND
neg.low.sideband
pos.low.sideband
pos.up.sideband
neg.up.sideband
MODULATION:
NCO_LP_SEL
FREQ_NCO
PHI_NCO
shows an overview of all register pages.
NCO_ON
MONITORING
Sync Mqmt
CONTROL
All information provided in this document is subject to legal disclaimers.
INV_SINC_SEL
INVERSE
SIN x / x
Rev. 1.1 — 10 October 2011
PAGE x02: MUTIPLES DEVICES SYNCHRONIZATION/INTERRUPTS
SYSREF
WEST
PAGE x00: INTERFACE DAC DSP
MINUS_3DB
CONTROL
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
IO0/IO1
MDS Managment
INTERRUPTS
PH_CORR_EN
CORRECTION
PH_CORR
PHASE
DAC_A_DGAIN
DAC_B_DGAIN
A_DGAIN_EN
CONTROL
B_DGAIN_E
LEVEL
I/Q DC
GAIN A
GAIN B
SYSREF
EAST
DAC1628D1G25
DAC_A_OFFSET
DAC_B_OFFSET
PAGE x01: DUAL DAC CORE
OFFSET A
OFFSET B
+
+
power
on/off
sleep
TEMPERATURE SENSOR
CLOCK DISTRIBUTION
∑
∑
CLOCK GENERATION
(PLL/BYPASS MODE)
CONTROL
CLOCKS
DACA
DACB
RESET
AUX.
AUX.
© NXP B.V. 2011. All rights reserved.
DAC
DAC
CLIPPING
CLIP_LVL
CLIP_EN
aaa-000281
aaa-000282
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