dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 103

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 123. Register MAIN_CTRL (address 00h)
Default values are shown highlighted.
Table 124. Register DCSMU_AUTO_CTRL (address 01h)
Default values are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
7 to 4
3
2
1
0
Bit
7
4
3
2
1
0
Symbol
POFF_RX[3:0]
NO_DCLK_REINIT
FULL_REINIT
FORCE_RST_DCLK
FORC_RST_WCLK
Symbol
MAN_PON_CTRL
FORCE_LOCK_DET
AUTO_QUICK_EN
AUTO_LOCK_DET_EN
RESERVED
AUTO_CAL_EQ
10.17.7.2 Page x0A bit definition detailed description
The tables in this section contain detailed descriptions of the page x0A registers.
Access
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Value
-
0
1
0
1
0
1
0
1
Value
0
1
0
1
0
1
0
1
-
0
1
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Description
reinitialization, digital clock select
quick/full reinitialization selection
Description
automatic control of the rx-phy power-up
automatic lock detection
reserved
automatic calibration equalizer
power-down of the physical lane receiver
digital clock reset
work clock reset
DCSMU auto-control
lock detection
bit 7 = lane 3
bit 6 = lane 2
bit 5 = lane 1
bit 4 = lane 0
full reinitialization with restart digital clock reset
full reinitialization without restart digital clock reset
quick reinitialization
full reinitialization
release digital clock reset
force digital clock reset
release work clock reset
force work clock reset
pon_rx-phy and pon_dacs controlled by DCSMU
manual control of pon_rx_phy and pon_dacs
no action
ignore internal lock detectors
do not enable rx-phy after power-up/spi-reset
enable rx-phy after power-up/spi-reset
disabled
enabled
disabled (use auto-zero)
enabled
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
103 of 133