dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 115

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

Table 148. Page 11 register allocation map
Address Register name
0
1
4
5
6
7
12 0Ch
13 0Dh
14 0Eh
15 0Fh
17 11h
25 19h
00h
01h
04h
05h
06h
07h
I_HS_REF_EN
I_HS_REF_POLY
_TRIM
I_HS_RX_CDR_
LOOP
I_HS_RX_CDR_
ENA_0
I_HS_RX_CDR_
ENA_1
I_HS_RX_EQ_
CNTRL
I_HS_RX_0_EQ_
OFS
I_HS_RX_1_EQ_
OFS
I_HS_RX_2_EQ_
OFS
I_HS_RX_3_EQ_
OFS
I_HS_RX_RT_
CNTRL
HS_RX_0_MON
10.17.8.3 Page x11 register allocation map
Table 148
R/W
R
R
R
R
R
R
R
R
R
R
R
R
shows an overview of all registers on page x11.
Bit 7
I_HS_RX_CDR_LOOP_RZ[2:0]
-
-
-
-
-
-
-
-
-
-
-
I_HS_RX0_
I_HS_RX1_
I_HS_RX2_
I_HS_RX3_
EQ_INPUT
EQ_INPUT
EQ_INPUT
EQ_INPUT
_SHORT
_SHORT
_SHORT
_SHORT
Bit 6
-
-
-
-
-
-
-
EQ_TEST_
I_HS_RX_
DUTY_EN
Bit 5
-
-
-
-
-
EQ_AUTO_
I_HS_RX_
ZERO_EN
Bit 4
-
-
-
-
-
-
Bit definition
I_HS_RX0_EQ_OFFSET[5:0]
I_HS_RX1_EQ_OFFSET[5:0]
I_HS_RX2_EQ_OFFSET[5:0]
I_HS_RX3_EQ_OFFSET[5:0]
I_HS_REF_POLY_TRIM[5:0]
I_HS_RX3_
I_HS_RX3_
I_HS_RX3_
I_HS_RX_3
DUTY_OUT
EQ_TEST_
HS_RX_0_
DATA_EN
CDR_EN
TRACK_
_RT_EN
EQ_EN
CDR_
Bit 3
-
-
I_HS_REF_
I_HS_RX2_
I_HS_RX2_
I_HS_RX2_
I_HS_RX_2
HS_RX_0_
TUNE_EN
DATA_EN
EQ_OFS_
CDR_EN
TRACK_
_RT_EN
EQ_EN
CDR_
Bit 2
POL
-
CALIBRATE
I_HS_REF_
I_HS_RX1_
I_HS_RX1_
I_HS_RX1_
I_HS_RX_1
REFCLOCK
HS_RX_0_
DATA_EN
CDR_EN
TRACK_
_RT_EN
EQ_EN
LOCK_
CDR_
Bit 1
_EN
-
I_HS_REF_
CDR_FACQ
I_HS_RX0_
I_HS_RX0_
I_HS_RX0_
I_HS_RX_0
HS_RX_0_
DATA_EN
CDR_EN
TRACK_
_RT_EN
EQ_EN
_BUSY
CDR_
Bit 0
EN
-
Default
Bin
0000
0101
0000
0000
0001
0111
0000
1111
0000
0000
0001
1111
0000
0000
0000
000
0000
0000
0000
0000
Hex
05h
00h
17h
0Fh
00h
1Fh
00h
00h
00h
00h